1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device including a memory cell array having a plurality of banks.
2. Description of Related Art
In a Double Data Rate 3 (DDR3) type Synchronous Dynamic Random Access Memory (SDRAM) having eight banks, eight banks BA0 to BA7 are arranged in two lines with four banks in each line, for example. The banks are intended to mean a plurality of memory areas having non-exclusive control relationship with one another. The banks are arranged in the order of the banks BA0, BA1, BA4, and BA5 in a first line and in the order of the banks BA2, BA3, BA6, and BA7 in a second line from one end (upper left end) to the other end (lower right end) of a chip. A data input/output terminal is arranged as an interface shared by the eight banks in an area between the lines (hereinafter, referred to as a “wiring area”).
Each of the banks BA0 to BA7 and the data input/output terminal are connected by a predetermined number of the read/write buses. As an example, when the number of data input/output terminals is eight, the number of prefetches is eight, and a burst length=4, the number of read/write buses required for each bank is obtained as 8×8/(8/4)=32. Hereinafter, description will be given on the assumption of this example.
Each of the 32 read/write buses for each bank is extracted from a main amplifier in the corresponding bank to the wiring area and wired to the data input/output terminal through a Y11 multiplexer related to Y11 being a part of a column address and a First In First Out (FIFO) circuit while joining with the read/write bus from another bank. Herein, the Y11 multiplexer is a circuit for realizing switching between ×4 operation (operation to input and output data using only four data input/output terminals) and ×8 operation (operation to input and output the data using all eight data input/output terminals). Also, the FIFO circuit realizes burst input/output.
When a connection relationship is specifically described, each group of the 32 read/write buses, extracted from each of the banks BA0, BA2, BA5, and BA7 located on furthest ends (upper left, lower left, upper right, and lower right) of the chip to the wiring area, extends in the wiring area in a chip longitudinal direction (x-direction) toward the center of the chip. Each group of the 32 read/write buses, extracted from each of the banks BA1, BA3, BA4, and BA6 located so as to be closer to the center of the chip (upper left, lower left, upper right, and lower right) in the wiring area, joins with the read/write buses extracted from the bank on the furthest end adjacent to the same in the wiring area. Each read/write bus thus extracted in the vicinity of the center of the chip is connected to the Y11 multiplexer in the vicinity of the center of the chip.
Four read/write buses are connected to each of the eight data input/output terminals. Thirty-two FIFO circuits for the read/write buses are provided and ends on a side of the Y11 multiplexer of the thirty-two FIFO circuits are connected to four Y11 multiplexers through the four read/write buses.
Japanese Patent Application Laid-Open No. 2009-015953 discloses a circuit configuration of the DDR3 type SDRAM in detail.
However, the read/write bus configured as described above has a problem in that high-speed operation cannot be performed. This is because a wiring length of the read/write bus increases to be substantially half a length of a longitudinal side (x-direction) of the chip for the four banks BA0, BA2, BA5, and BA7 located on the furthest ends of the chip, so that a load (parasitic capacitance of the read/write bus) increases and a signal waveform is rounded.
On the other hand, it is possible to inhibit the rounding of the signal waveform by inserting an intermediate buffer between the banks BA0 and BA1, between the banks BA2 and BA3, between the banks BA5 and BA4, and between the banks BA7 and BA6. However, the number of stages of the intermediate buffer is different for each bank as seen from the data input/output terminal with such a configuration, so that skew is generated between the banks on the basis of the FIFO circuit at the time of reading, for example. Especially, this is the skew of the data between the banks, which share the read/write bus. For example, time required for a plurality of data corresponding to a bank 0 and a bank 1 to arrive at the FIFO circuit is different, and this is the skew indicating the plurality of data. Therefore, although the rounding of the signal waveform may be inhibited, the high-speed operation cannot be realized after all.